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2013-11-13 来源: 类别: 更多范文
FPGA 综合实验
一．摘要：
利用Matlab产生一个周期的非负正弦波，然后对其采样，取1024 点8 位数据。在QuartusII中利用MegaWizard 生成一个1024*8bits 的存储器（ram/rom），并利用上述正弦波数据来初始化此存储器。编写VHDL 程序，按一定的方式（如顺序）将存储器中的数据读出并输出到DA 端口，编译，仿真。最后为工程添加一个signaltap II 文件，设置参数，编译，无错后下载到目标板，并在signaltap II 中观看输出到DA 端口的数据及波形。
二．实验内容：
1.利用matalb 产生正弦波数据
matlab中命令：
x = 0 : 2 * pi / 1024 : 2 * pi;
y = 128 * (1 + sin(x));
sin_table = uint8(y);
2. 创建Quartus II 工程并添加一个存储器初化文件
mystorage_inst : mystorage PORT MAP (
address => address_sig,
clock => clock_sig,
data => data_sig,
wren => wren_sig,
q => q_sig
);
3. 利用MegaWizard 产生存储器
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: mystorage.vhd
-- Megafunction Name(s):
-- altsyncram
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 178 04/27/2006 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY mystorage IS
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END mystorage;
ARCHITECTURE SYN OF mystorage IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
indata_aclr_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL;
wrcontrol_aclr_a : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q "NONE",
indata_aclr_a => "NONE",
init_file => "memory.mif",
intended_device_family => "Cyclone",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 1024,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 10,
width_a => 8,
width_byteena_a => 1,
wrcontrol_aclr_a => "NONE"
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
4. 编写存储器读控制程序
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
entity memory is
port( clk: in std_logic;
rst: in std_logic;
da_out : out std_logic_vector(7 downto 0)
);
end memory;
architecture arch_memory of memory is
component mystorage is
PORT
(
address : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END component;
signal add_sig : STD_LOGIC_VECTOR (9 DOWNTO 0);
signal data_in_sig: std_logic_vector(7 downto 0);
signal clk_sig: std_logic;
constant wren_sig: std_logic:='0';
signal q_sig: STD_LOGIC_VECTOR (7 DOWNTO 0);
begin
mystorage_inst1 : mystorage PORT MAP (
address => add_sig,
clock => clk_sig,
data => data_in_sig,
wren => wren_sig,
q => q_sig
);
clk_sig
